1. Field of the Invention
The present invention relates to a semiconductor test system for testing a semiconductor integrated circuit, a semiconductor test method using the system, a semiconductor integrated circuit applicable to the test method and a method of forming a wiring pattern of the semiconductor integrated circuit.
2. Description of the Background Art
FIG. 6 is a schematic view of a conventional semiconductor test system. In FIG. 6, numeral 5 denotes a tester. The tester is connected to a plurality of probes 3 through connecting wires 4. Numeral 1 denotes a semiconductor integrated circuit to be tested by the tester 5. The semiconductor integrated circuit 1 comprises input pads 2a, output pads 2b and a power supply pad 2c serving as external terminals. These pads 2a, 2b and 2c are in contact with the probes 3, respectively.
In the semiconductor test system, an electric signal according to a test pattern is inputted to the input pad 2a from the tester 5, consequently an output signal corresponding to the function of the semiconductor integrated circuit 1 is outputted from the output pad 2b. The tester 5 detects the output signal and compares it with an expected value, thus testing the semiconductor integrated circuit 1.
FIG. 5 illustrates an example of a mask pattern of the semiconductor integrated circuit, such as a gate array, to be tested by the above conventional semiconductor test system. In FIG. 5, a gate 16 is disposed between a drain region 13 and a source region 14. Covering the drain region 13 and the source region 14, formed are a first layer metal wiring 10, a second layer metal wiring 11 and a third layer metal wiring 12. Numeral 15 denotes contact holes for interconnecting these wirings and regions.
In the conventional semiconductor test system, as described above, a test of the semiconductor integrated circuit depends on only the electric signal input to the input pads according to the test pattern, so that it is required to increase the number of the test patterns as the semiconductor integrated circuit becomes larger in scale and higher in integration. Moreover, when a degree of enlargement and integration is much higher, only the increase of the test patterns can not necessarily cause to improve a detection coverage, and there may be a case where detecting a fault is partly impossible. Providing a dedicated circuit for testing within the semiconductor integrated circuit is a reliable test method, but it is accompanied by the increases in space and cost.